System-on-a-Chip Verification: Methodology and Techniques
Prakash Rashinkar, Peter Paterson, Leena Singh
The combination of previously separate elements into one lone chip presents engineers with challenges to traditional verification approaches. This guide provides a series of tools and techniques that can be employed for system-on-chip (SOC) verification and design error reduction. The authors, who work for Cadence Design Systems, walk through system level and block verification, simulation, hardware/software co-verification, static netlist verification, and physical verification technologies. Particular attention is paid to newer techniques< - >such as testbench migration, formal model and equivalence checking, linting, and code coverage< - >and the material is illustrated by examples based on a Bluetooth SOC design.
カテゴリー:
年:
2000
版:
1
出版社:
Springer
言語:
english
ページ:
393
ISBN 10:
0306469952
ISBN 13:
9780792372790
ファイル:
PDF, 4.28 MB
IPFS:
,
english, 2000